Brand/ Manufacturer:
SiemensDimensions:
27.9 x 2.5 x 20.3 cmWeight:
0.8 kgCountry of Origin: :
GermanyDescription:
Interface Module
Mfr. Part Number: |
PS02-3005 |
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Manufacturer: |
Siemens |
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Description: |
Get the best deals for PS02-3005 |
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Full Description: |
"Permanent System Load" block is configured. The PSL block is configured in any cyclic task in the CPU to be investigated. |
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SIEMENS PS02-3005
Extract each inverter module from the cubicle as follows:
(1) Open the door of the inverter cubicle.
(2) Remove the shroud covering the upper part of the cubicle.
(3) Open the transparent cover on the front of the inverter module and disconnect the fibre optic cables.
Move the cables aside.
(4) Remove the L-shaped DC busbars on top of the module.
(5) Disconnect the terminal block (X50) next to the DC busbars
Siemens PLC Board PS02-3005
The precise CPU utilization can only be determined when the PSL "Permanent System Load" block is configured. The PSL block is configured in any cyclic task in the CPU to be investigated.
It has 5 outputs (Y1..5) which display the actual utilization of the individual tasks in the form of a load factor. The displayed factor should not exceed 1.0 (100%). Values exceeding 1.0 indicate that a CPU is overloaded.
Further, the PSL block has 5 inputs (T1..5) which, for each task, can be used to simulate an additional load in milliseconds (ms). It is then possible to read how such a load affects the utilization of the individual tasks at the outputs. The utilization is determined by measuring the task run times and then dividing this by the actual sampling time. Higher priority tasks occur within the run time of a task which extends the run time and noticeably increases the utilization. Thus, by just adding these values, it isn’t possible to obtain an overall utilization level.
In addition to the configurable interrupt tasks, the cyclic tasks are interrupted, especially by communication interrupts. These interrupts to ensure that, for example, the data to be transmitted and received via the serial interfaces is processed before new data is received. Transmit- and receive interrupts such as these can occur independently of the configured cycle time of the appropriate communication blocks at almost any instant in time. As a result of this, and the unpredictable occurrence of interrupt tasks, if the processor utilization is extremely high, each cyclic task can generate one or several cycle errors due to task back-up.
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